1. Field of the Invention
The present invention generally relates to apparatuses and methods for judging the validity of a transfer data that makes an error detection in data processing systems which need to make a high-speed and large-volume data transfer with a high reliability, and more particularly to an apparatus and a method for judging the validity of the transfer data using a check code in a data processing system in which a data block including the data and the check code with respect to the data is disassembled into a plurality of frames and transferred. The present invention also relates to a storage apparatus and a storage control apparatus that employ the apparatus or method described above, a computer-readable program for causing a computer to judge the validity of the transfer data by the method described above, and a computer-readable storage medium which stores such a computer-readable program.
2. Description of the Related Art
Recently, fiber channels are generally used as a means for making a high-speed and large-volume data transfer between a host computer and a storage apparatus. The storage apparatus includes a storage unit such as a disk unit (or disk drive) that is shared by a plurality of host computers, and a storage control apparatus that controls the data transfer between the host computer and the storage apparatus.
The data of the host computer at the sending end is disassembled into a plurality of frames of up to 2 kbytes and transferred on a fiber channel link, and is assembled back into the original data in the storage apparatus at the receiving end. Each of the frames that are transferred is error-protected by a Cyclic Redundancy Check (CRC), so that a highly reliable data transfer can be made.
However, there are demands to further improve the reliability of the data transfer, depending on the situation. In order to satisfy such demands, there is a protection method that protects the entire data prepared in the host computer, in addition to the error protection provided by the CRC for each frame. A computation according to a predetermined algorithm is carried out using the data to be protected, and a result obtained by this computation is used as the check code. The CRC code is one example of the check code. The CRC code or other check codes, such as cyclic codes, may be used depending on the situation.
According to the above protection method, a host computer adds a check code 102 to a user data 101, so as to obtain 1 data block 103 that is to be sent as shown in FIG. 1. FIG. 1 is a diagram showing the data protection by the check code. On the fiber channel link, the data block 103 is disassembled into a plurality of frames 104 (104a, 104b, 104c and 104c), and each frame 104 is protected by the CRC and transferred to the storage control apparatus. Normally, the check code 102 is smaller that the data amounting to 1 frame, and for this reason, the check code 102 is accommodated within the last frame 104 and transferred.
The storage apparatus carries out the CRC check for each of the received frames 104, and assembles the received frames 104 back into the original data block 103. Then, the storage apparatus carries out a computation with respect to the user data 101 according to the same algorithm that was used by the host computer to generate the check code 102. A result of this computation carried out in the storage apparatus should become the same as the check code 102 that is added by the host computer, and thus, by comparing the result of this computation and the check code 102, it is possible to judge the validity of the user data 101.
FIG. 2 is a diagram showing a structure of a data processing system employing the protection method described above. The data processing system shown in FIG. 2 includes one or more host computers 111, a communication network 112, a storage control apparatus 113, and one or more disk drives 114.
The host computer 111 is connected to the storage control apparatus 113 via the communication network 112, and the disk drive 114 is connected to the storage control apparatus 113. The storage control apparatus 113 and the disk drive 114 form a storage apparatus. The communication network 112 corresponds to the fiber channel link, for example, and is provided with a switch. Generally, a plurality of host computers 111 are connected to the communication network 112. The storage control apparatus 113 includes a processor 121, a controller 122 and a data buffer 123, and the controller 122 includes a check code judging circuit 131 and a CRC check circuit 132. The storage control apparatus 113 includes an interface (not shown) with respect to the host computer 111 and the disk drive 114, and receives the data from the host computer 111 via the communication network 112.
As shown in FIG. 1, the frame of the fiber channel includes a header part, a data part and a CRC code, and when the controller 122 receives the frame, the CRC check circuit 132 first confirms whether or not an error exists in the received frame. At the same time as this confirmation, the controller 122 stores the data part of the received frame in the data buffer 123, and delivers the header part to the processor 121. The header part of the frame includes information that is necessary to know the data block to which the frame belongs and to assemble the original data.
The storage control apparatus 113 repeats the operation described above, and successively receives the frames from the host computer 111. When the entire data block of one user is stored within the data buffer 123, the processor 121 starts the check code judging circuit 131.
The check code judging circuit 131 repeats an operation of reading the data block from the data buffer 123 a predetermined amount (for example, 4 bytes) at a time, and applying a predetermined algorithm to the read data, so as to generate the check code of the data block. Then, the check code judging circuit 131 judges the validity of the generated check code, and notifies a result of this judgement to the processor 121.
The applicant is aware of the following prior art references 1) through 6).
1) Japanese Laid-Open Patent Application No. 2001-144629
2) Japanese Laid-Open Patent Application No. 5-091072
3) Japanese Laid-Open Patent Application No. 5-035624
4) U.S. Pat. No. 5,630,054
5) Japanese Laid-Open Patent Application No. 5-260125
6) Japanese Laid-Open Patent Application No. 11-45157
The prior art reference 1) is related to an error correction apparatus for an optical disk, the prior art reference 2) is related to a data transfer system using CRC between terminals, the prior art reference 3) is related to a radio data transfer using an error correction code, and the prior art reference 4) is related to an error judgement of a storage apparatus using CRC. The prior art reference 5) is related to a data transfer control system for detecting a frame in which an error is generated during transfer and for resending the frame. The prior art reference 6) is related to a data transfer method for preventing considerable throughput deterioration and system halt caused by reissuance of a command when the CRC error is temporarily generated frequently during the data transfer.
The following problems are encountered in the conventional check code judging method described above.
According to the conventional check code judging sequence, the check code judging circuit is started to judge the check code after all of the frames of the data block of the user data are received. For this reason, it takes a considerably long time for the judgement to end. In order to end this judgement more quickly, it is conceivable to start the check code judging circuit every time the frame is received, and to compute the intermediate result up to the received data.
But on the fiber channel link, the frames of one user data are not necessarily transferred in succession, and as shown in FIG. 3, the user data from a plurality of host computers are disassembled into frames and transferred in an interleaved state. FIG. 3 is a diagram for explaining the data transfer from the plurality of host computers.
In the particular case shown in FIG. 3, the data blocks 141a, 141b and 141c (user data A, B and C) from the host computers 111a, 111b and 111c are respectively disassembled into 3 frames and transferred to the storage control apparatus 113. The original user data A, B and C are assembled from the data accommodated within these frames, and stored in the disk drive 114.
In this case, if the check code judging circuit is started every time the frame is received, the judgement of the check code with respect to 1 user data (for example, the user data A) can be ended quickly, but during this time, the remaining user data (for example, the user data B and C) cannot be input to the check code judging circuit. Consequently, the judgement with respect to the remaining user data must wait until the judgement with respect to the 1 user data ends, and this conceivable method does not sufficiently solve the problem of the judgement taking a considerably long time to end.